Conventionally, an optical-sensor-equipped display device has been proposed that is provided with photodetecting elements such as photodiodes in its pixels and thereby is capable of detecting a brightness of external light and capturing an image of an object approaching its display panel.
Such an optical-sensor-equipped display device is supposed to be used as a display device for two-way communication, or a display device having a touch panel function. In the case of a conventional optical-sensor-equipped display device, when known constituent elements such as signal lines and scanning lines, TFTs (thin film transistors), and pixel electrodes are formed on the active matrix substrate through semiconductor processing, photodiodes and the like are formed on the active matrix substrate through the same processing (see JP 2006-3857 A).
As a conventional optical sensor formed on an active matrix substrate, an exemplary configuration disclosed in WO2007/145346 and WO2007/145347 is shown in FIG. 62. The conventional optical sensor shown in FIG. 62 is composed mainly of a photodiode D1, a capacitor C2, and a transistor M2. To an anode of the photodiode D1, a line RST for supplying a reset signal is connected. To a cathode of the photodiode D1, one of electrodes of the capacitor C2 and a gate of the transistor M2 are connected. A drain of the transistor M2 is connected to a line VDD, and a source thereof is connected to a line OUT. The other electrode of the capacitor C2 is connected to a line RWS for supplying a readout signal.
In this configuration, a sensor output VPIX according to an amount of light received by the photodiode D1 can be obtained by supplying a reset signal and a readout signal to the line RST and the line RWS, respectively, at respective predetermined timings. Here, an operation of the conventional optical sensor as shown in FIG. 62 is explained with reference FIG. 63. It should be noted that in FIG. 63, a low level (e.g., −7 V) of the reset signal is denoted by “VRST.L”, a high level (e.g., 0 V) of the reset signal is denoted by “VRST.H”, a low level (e.g., 0 V) of the readout signal is denoted by “VRWS.L”, and a high level (e.g., 15 V) of the readout signal is denoted by “VRWS.H”.
First, when the high-level reset signal VRST.H is supplied to the line RST, the photodiode D1 is forward-biased, and a potential VINT of the gate of the transistor M2 is therefore expressed by the following formula (1):VINT=VRST.H−VF  (1)where VF is a forward voltage of the photodiode D1. Since VINT herein is lower than a threshold voltage of the transistor M2, the transistor M2 is non-conductive during a reset period.
Next, the reset signal becomes the low level potential VRST.L again (at the timing of tRST in FIG. 63), and thereby a photoelectric current integration period (a sensing period that is a period denoted by TINT shown in FIG. 63) starts. In the integration period, a photoelectric current proportional to an amount of light incident on the photodiode D1 flows out of the capacitor C2, whereby the capacitor C2 is discharged. Accordingly, the potential VINT of the gate of the transistor M2 at the end of the integration period is expressed by the following formula (2):VINT=VRST.H−VF−ΔVRST·CPD/CTOTAL−IPHOTO·TINT/CTOTAL  (2)where ΔVRST represents a height of a pulse of the reset signal (VRST.H−VRST.L), IPHOTO represents a photoelectric current of the photodiode D1, and TINT represents a duration of the integration period. CPD represents a capacitance of the photodiode D1. CTOTAL represents a sum of a capacitance of the capacitor C2, the capacitance CPD of the photodiode D1, and a capacitance CTFT of the transistor M2. During the integration period also, since the VINT is lower than the threshold voltage of the transistor M2, the transistor M2 is non-conductive.
After the integration period ends, at the timing tRWS shown in FIG. 63, the readout signal RWS rises, and the readout period thereby starts. It should be noted that the readout period continues while the readout signal RWS remains at the high level. Here, the injection of charges into the capacitor C2 occurs. As a result, the potential VINT of the gate of the transistor M2 is expressed by the following formula (3):VINT=VRST.H−VF−ΔVRST·CPD/CTOTAL−IPHOTO·TINT/CTOTAL+ΔVRWS·CINT/CTOTAL  (3)
ΔVRWS is a height of a pulse of the readout signal (VRST.H−VRWS.L). With this, the potential VINT of the gate of the transistor M2 becomes higher than the threshold voltage thereof, and this causes the transistor M2 to become conductive. Thus, the transistor M2, together with the bias transistor M3 provided at an end of the line OUT in each column, functions as a source-follower amplifier. In other words, the sensor output voltage VPIX from the transistor M2 is proportional to an integral of the photoelectric current of the photodiode D1 during the integration period.
It should be noted that in FIG. 63, the waveform indicated by a solid line represents variation of the potential VINT in the case where light incident on the photodiode D1 is small in amount. The waveform indicated by a broken line represents variation of the potential VINT in the case where saturation-level light is incident on the photodiode D1. ΔVSIG shown in FIG. 63 represents a potential difference proportional to an amount of light incident on the photodiode D1. ΔVINT shown in FIG. 63 is an amount by which the potential VINT is boosted by the application of the readout signal from the line RWS to the optical sensor during the readout period.